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rev. 0.2 / jul. 2008 1 204pin ddr3 sdram sodimms ** contents are subject to ch ange without prior notice. ddr3 sdram unbuffered sodimms based on 1gb a version hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c
rev. 0.2 / jul. 2008 2 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c revision history revision no. history draft date remark 0.01 initial draft sep. 2007 preliminary 0.02 added idd, corrected typos mar. 2008 preliminary 0.03 halogen-free added may. 2008 preliminary 0.1 initial specification release may 2008 0.2 added outline: dimms with thermal sensor, corrected typos jul. 2008
rev. 0.2 / jul. 2008 3 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table of contents 1. description 1.1 device features and ordering information 1.1.1 features 1.1.2 ordering information 1.2 speed grade & key parameters 1.3 address table 2. pin architecture 2.1 pin definition 2.2 input/output functional description 2.3 pin assignment 3. functional block diagram 3.1 512mb, 64mx64 module(1rank of x16) 3.2 1gb, 128mx64 module(2rank of x16) 3.3 2gb, 256mx64 module(2rank of x8) 4. absolute maximum ratings 4.1 absolute maximum dc ratings 4.2 operating temperature range 5. ac & dc operating conditions 5.1 recommended dc operating conditions 5.2 dc & ac logic input levels 5.2.1 for single-ended signals 5.2.2 for differential signals 5.2.3 differential input cross point 5.3 slew rate definition 5.3.1 for ended input signals 5.3.2 for differential input signals 5.4 dc & ac output buffer levels 5.4.1 single ended dc & ac output levels 5.4.2 differential dc & ac output levels 5.4.3 single ended output slew rate 5.4.4 differential ended output slew rate 5.5 overshoot/undershoot specification 5.5.1 address and control overshoo t and undershoot specifications 5.5.2 clock,data,strobe and mask over shoot and undershoot specifications 5.6 input/output capacitance & ac parametrics 5.7 idd specifications & measurement condtiions 6 . electrical characteristics and ac timing 6.1 refresh parameters by device density 6.2 ddr3 standard speed bins and ac para 7 . dimm outline diagram 7.1 512mb, 64mx64 module(1rank of x16) 7.2 1gb, 128mx64 module(2rank of x16) 7.3 2gb, 256mx64 module(2rank of x8)
rev. 0.2 / jul. 2008 4 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c ? vdd=vddq=1.5v ? vddspd=3.0v to 3.6v ? fully differential clock inputs (ck, /ck) operation ? differential data strobe (dqs, /dqs) ? on chip dll align dq, dqs and /dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, and (11) supported ? programmable additive latency 0, cl-1 and cl-2 sup- ported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst leng th 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8 banks ? 8k refresh cycles /64ms ? ddr3 sdram package : jedec standard 82ball fbga(x4/x8) , 100ball fbga (x16) with support balls ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? 8 bit pre-fetch 1. description this hynix unbuffered small outline dual in-line memory mo dule(sodimm) series consists of 1gb a version. ddr3 sdrams in fine ball grid array(fbga) packages on a 204 pin glass-epoxy substrate. this ddr3 unbuffered sodimm series based on 1gb a version provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. it is suitble for ea sy interchange and addition. 1.1 device features & ordering information 1.1.1 features
rev. 0.2 / jul. 2008 5 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 1.1.2 ordering information two types, with integrated thermal sensor and with no thermal sensor, exist, in each configuration. part name density organization # of drams # of ranks materials hmt164s6afp6c-s6/s5/g8/g7/h9/h8 512mb 64mx64 4 1 lead free hmt164s6afr6c-s6/s5/g8/g7/h9/h8 512mb 64mx64 4 1 halogen free hmt112s6afp6c-s6/s5/g8/g7/h9/h8 1gb 128mx64 8 2 lead free hmt112s6afr6c-s6/s5/g8/g7/h9/h8 1gb 128mx64 8 2 halogen free hmt125s6afp8c-s6/s5/g8/g7/h9/h8 2gb 256mx64 16 2 lead free hmt125s6afr8c-s6/s5/g8/g7/h9/h8 2gb 256mx64 16 2 halogen free
rev. 0.2 / jul. 2008 6 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 1.2 speed grade & key parameters 1.3 address table mt/s ddr3-800 ddr3-1066 ddr3-1333 unit grade -s6 -s5 -g8 -g7 -h9 -h8 tck(min) 2.5 1.875 1.5 ns cas latency 658798tck trcd(min) 15 12.5 15 13.125 13.5 12 ns trp(min) 15 12.5 15 13.125 13.5 12 ns tras(min) 37.5 37.5 37.5 37.5 36 36 ns trc(min) 52.5 50 52.5 50.625 49.5 48 ns cl-trcd-trp 6-6-6 5-5-5 8-8-8 7-7-7 9-9-9 8-8-8 tck 512mb 1gb 2gb organization 64m x 64 128m x 64 256m x 64 refresh method 8k/64ms 8k/64ms 8k/64ms row address a0-a12 a0-a12 a0-a13 column address a0-a9 a0-a9 a0-a9 bank address ba0-ba2 ba0-ba2 ba0-ba2 page size 2kb 2kb 1kb # of rank 12 2 # of device 48 16
rev. 0.2 / jul. 2008 7 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 2. pin architecture 2.1 pin definition pin name description pin name description ck[1:0] clock inputs, positive line 2 dq[63:0] data input/output 64 ck [1:0] clock inputs, negative line 2 dm[7:0] data masks 8 cke[1:0] clock enables 2 dqs[7:0] data strobes 8 ras row address strobe 1 dqs [7:0] data strobes complement 8 cas column address strobe 1 reset reset pin 1 we write enable 1 test logic analyzer specific test pin (no connect on sodimm) 1 s [1:0] chip selects 2 event temeprature event pin 1 a[9:0], a11, a[15:13] address inputs 14 v dd core and i/o power 18 a10/ap address input/autoprecharge 1 v ss ground 52 a12/ bc address input/burst stop 1 v ref dq input/output reference 2 ba[2:0] sdram bank address 3 v ref ca odt [1:0] on-die termination control 2 v dd spd spd and temp sensor power 1 scl serial presence detect(spd) clock input 1 vtt termination voltage 2 sda spd data input/output 1 nc reserved for future use 2 sa [1:0] spd address 2 total 204
rev. 0.2 / jul. 2008 8 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 2.2 input/output functional description symbol type polarity function ck0/ ck 0 ck1/ ck 1 input cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop (dll) cir - cuit is driven from the clock inputs and ou tput timing for read operations is synchro - nized to the input clock. cke[1:0] input active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] input active low enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new com - mands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1. ras , cas , we input active low when sampled at the cross point of the ri sing edge of ck and falling edge of ck , sig - nals cas , ras , and we define the operation to be executed by the sdram. ba[2:0] input - selects which ddr3 sdram internal bank of eight is activated. odt[1:0] input active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr3 sdram mode register. a[9:0], a10/ap , a11, a12/bc , a[15:13] input - during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operat ion at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0- ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. a12( bc ) is sampled during read and write commands to determine if burst chop (on-thefly) will be performed (high, no burst chop; low, burst chopped) dq[63:0] in/out - data input/output pins. dm[7:0] input active high the data write masks, associated with on e data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs[7:0], dqs [7:0] in/out cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdrams and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs .
rev. 0.2 / jul. 2008 9 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c v dd, v dd spd, v ss, supply power supplies for core, i/o, serial presence detect, temp sensor, and ground for the module. v ref dq, v ref ca supply reference voltage for sstl15 inputs. sda in/out this is a bidirectional pin used to transfer data into or out of the spd eeprom and temp sensor. a resistor must be connected from the sda bus line to v dd spd on the system planar to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom and temp sensor. sa[1:0] input address pins used to select the serial presence detect and temp sensor base address. test in/out the test pin is reserved for bus analysis tools and is not connected on normal memory modules (so-dimms). event wire or out active low the event pin is reserved for use to flag critical module temperature. a resistor may be connected from event bus line to vd dspd on the system planar to act as a pullup. reset in active low this signal resets the ddr3 sdram symbol type polarity function
rev. 0.2 / jul. 2008 10 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 2.3 pin assignment pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side pin # front sid pin # back side 1 v ref dq 2 v ss 53 dq19 54 v ss 105 v dd 106 v dd 157 dq42 158 dq46 3 v ss 4 dq4 55 v ss 56 dq28 107 a10/ap 108 ba1 159 dq43 160 dq47 5 dq0 6 dq5 57 dq24 58 dq29 109 ba0 110 ras 161 v ss 162 v ss 7 dq1 8 v ss 59 dq25 60 v ss 111 v dd 112 v dd 163 dq48 164 dq52 9 v ss 10 dqs 0 61 v ss 62 dqs 3 113 we 114 s 0 165 dq49 166 dq53 11 dm0 12 dqs0 63 dm3 64 dqs3 115 cas 116 odt0 167 v ss 168 v ss 13 v ss 14 v ss 65 v ss 66 v ss 117 v dd 118 v dd 169 dqs 6 170 dm6 15 dq2 16 dq6 67 dq26 68 dq30 119 a13 2 120 odt1 171 dqs6 172 v ss 17 dq3 18 dq7 69 dq27 70 dq31 121 s 1 122 nc 173 v ss 174 dq54 19 v ss 20 v ss 71 v ss 72 v ss 123 v dd 124 v dd 175 dq50 176 dq55 21 dq8 22 dq12 73 cke0 74 cke1 125 test 126 v ref ca 177 dq51 178 v ss 23 dq9 24 dq13 75 v dd 76 v dd 127 v ss 128 v ss 179 v ss 180 dq60 25 v ss 26 v ss 77 nc 78 a15 2 129 dq32 130 dq36 181 dq56 182 dq61 27 dqs 1 28 dm1 79 ba2 80 a14 2 131 dq33 132 dq37 183 dq57 184 v ss 29 dqs1 30 reset 81 v dd 82 v dd 133 v ss 134 v ss 185 v ss 186 dqs 7 31 v ss 32 v ss 83 a12/ bc 84 a11 135 dqs 4 136 dm4 187 dm7 188 dqs7 33 dq10 34 dq14 85 a9 86 a7 137 dqs4 138 v ss 189 v ss 190 v ss 35 dq11 36 dq15 87 v dd 88 v dd 139 v ss 140 dq38 191 dq58 192 dq62 37 v ss 38 v ss 89 a8 90 a6 141 dq34 142 dq39 193 dq59 194 dq63 39 dq16 40 dq20 91 a5 92 a4 143 dq35 144 v ss 195 v ss 196 v ss 41 dq17 42 dq21 93 v dd 94 v dd 145 v ss 146 dq44 197 sa0 198 event 43 v ss 44 v ss 95 a3 96 a2 147 dq40 148 dq45 199 vdd spd 200 sda 45 dqs 2 46 dm2 97 a1 98 a0 149 dq41 150 v ss 201 sa1 202 scl 47 dqs2 48 v ss 99 v dd 100 v dd 151 v ss 152 dqs 5 203 v tt 204 v tt 49 v ss 50 dq22 101 ck0 102 ck1 153 dm5 154 dqs5 51 dq18 52 dq23 103 ck0 104 ck1 155 v ss 156 v ss nc = no connect; rfu = reserved future use 1. test(pin 125) is reserved for bus analysis probes and is nc on normal memory modules. 2. this address might be connected to nc balls of the dram s (depending on density); ei ther way they will be con - nected to the termination resistor.
rev. 0.2 / jul. 2008 11 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 3. functional block diagram 3.1 512mb, 64mx64 modu le(1rank of x16) dqs1 dqs1 dm1 dq [8:15] dqs0 dqs0 dm0 dq [0:7] ldqs ldqs ldm dq [0:7] d0 udqs udqs udm dq [8:15] a2 te m p s e n s o r sda d0?d3 v dd spd spd/ts d0?d3 v ref ca scl v tt d0?d3 v dd event ras cas s0 we ck0 ck0 cke0 odt0 a[o:n]/ba[o:n] 240ohm zq +/-1% dqs3 dqs3 dm3 dq [24:31] dqs2 dqs2 dm2 dq [16:23] ldqs ldqs ldm dq [0:7] d1 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs5 dqs5 dm5 dq [40:47] dqs4 dqs4 dm4 dq [32:39] ldqs ldqs ldm dq [0:7] d2 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs7 dqs7 dm7 dq [56:63] dqs6 dqs6 dm6 dq [48:55] ldqs ldqs ldm dq [0:7] d3 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% vtt vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] vdd a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 odt1 s1 event reset d0?d3, spd, temp sensor d0?d3 d0?d3 terminated at near card edge nc nc temp sensor d0-d3 d0 d1 d2 d3 vtt notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relation- ships are maintained as shown address and control lines rank 0 the spd may be integrated with the temp sensor or may be a separate component
rev. 0.2 / jul. 2008 12 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 3.2 1gb, 128mx64 module(2rank of x16) dqs1 dqs1 dm1 dq [8:15] dqs0 dqs0 dm0 dq [0:7] ldqs ldqs ldm dq [0:7] d0 udqs udqs udm dq [8:15] ras cas s0 we ck0 ck0 cke0 odt0 a[o:n]/ba[o:n] 240ohm zq +/-1% dqs3 dqs3 dm3 dq [24:31] dqs2 dqs2 dm2 dq [16:23] ldqs ldqs ldm dq [0:7] d1 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs5 dqs5 dm5 dq [40:47] dqs4 dqs4 dm4 dq [32:39] ldqs ldqs ldm dq [0:7] d2 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% dqs7 dqs7 dm7 dq [56:63] dqs6 dqs6 dm6 dq [48:55] ldqs ldqs ldm dq [0:7] d3 udqs udqs udm dq [8:15] ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] vdd ldqs ldqs ldm dq [0:7] d4 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d5 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d6 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d7 udqs udqs udm dq [8:15] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck1 ck1 cke1 odt1 s1 vdd a2 te m p s e n s o r sda d0?d7 v dd spd spd/ts d0?d7 v ref ca scl v tt d0?d7 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 event reset d0?d7, spd, temp sensor d0?d3 d0?d7 temp sensor d0-d7 notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relation- ships are maintained as shown address and control lines rank 0 the spd may be integrated with the temp sensor or may be a separate component d0?d3 d0?d7 d0 d1 d2 d3 vtt d4 d5 d6 d7 vtt v1 v2 v4 v3 v1 v2 v4 v3 rank 1 vtt vtt
rev. 0.2 / jul. 2008 13 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 3.3 2gb, 256mx64 module(2rank of x8) dqs3 dqs3 dm3 dq[24:31] dqs dqs dm dq [0:7] d11 ras cas s1 we ck1 ck1 cke1 odt1 a[o:n]/ba[o:n] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d3 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck0 ck0 cke0 odt0 s0 a2 temp se ns or sda d0?d15 v dd spd spd/ts d0?d15 v ref ca scl v tt d0?d15 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 cke0 cke1 d0?d15, spd, temp sensor d0?d7 d8?d15 d0-d7 d8-d15 notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relationships are ma intained as shown rank 0 d0?d7 d8?d15 rank 1 dqs1 dqs1 dm1 dq[8:15] dqs dqs dm dq [0:7] d1 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d9 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs0 dqs0 dm0 dq[0:7] dqs dqs dm dq [0:7] d0 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d8 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs4 dqs4 dm4 dq[32:39] dqs6 dqs6 dm6 dq[48:55] dqs7 dqs7 dm7 dq[56:43] dqs5 dqs5 dm5 dq[40:47] vtt vtt vdd vdd cterm cterm d12 d4 dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d6 d14 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm d7 d15 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm dqs2 dqs2 dm2 dq[6:23] dqs dqs dm dq [0:7] d2 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d10 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d5 d13 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm s0 odt0 s1 odt1 event reset d0?d7 d8?d15 temp sensor d0-d15 d0?d7 d8?d15 the spd may be integrated with the temp sensor or may be a separate component d0 v1 v9 d1 d11 d2 d13 d4 d14 d15 d9 d8 d10 d3 d12 d5 d7 d6 vtt v1 v2 v3 v4 v5 v6 v8 v7 v6 v8 v7 v5 v9 v1 v4 v3 v2
rev. 0.2 / jul. 2008 14 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 4. absolute maximum ratings 4.1 absolute maxi mum dc ratings 4.2 dram component ope rating temperature range symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v 1,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v 1 tstg storage temperature -55 to +100 1, 2 1. stresses greater than those listed under ?absolut e maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the device at these or any other conditions above those indicated in the oper ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each ot her at all times;and vref must be not greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes toper normal temperature range 0 to 85 ,2 extended temperature range 85 to 95 1,3 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperat ures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions 3. some applications require operation of the dr am in the extended temperature range between 85 ? and 95 ? case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for some devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extend ed temperature range. please refer to supplier data sheet and/ or the dimm spd for option avail ability. b) if self-refresh operation is required in the extend ed temperature range, than it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0band mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).
rev. 0.2 / jul. 2008 15 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5. ac & dc operating conditions 5.1 recommended dc operating conditions 5.2 dc & ac logic input levels 5.2.1 dc & ac logic input levels for single-ended signals the dc-tolerance limits and ac-noise limits for the refere nce voltages vrefca and vrefdq are illustrated in figure 6.2.1. it shows a valid reference voltage vref(t) as a fu nction of time. (vref stands for vrefca and vrefdq like - wise).vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. furthermore vref(t) may temporarily deviate from vref(dc) by no more than +/- 1% vdd. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac paramaters are measured with vdd abd vddq tied together. symbol parameter ddr3-800, ddr3-1066, ddr3-1333 unit notes min max vih(dc) dc input logic high vref + 0.100 - v 1, 2 vil(dc) dc input logic low vref - 0.100 v 1, 2 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 vrefdq(dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 vrefca(dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd v 1. for dq and dm, vref = vrefdq. for inpu t ony pins except reset#, vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on vref may not allow vref to deviate from vref(dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). for reference: approx. vdd/2 +/- 15 mv.
rev. 0.2 / jul. 2008 16 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c < figure 6.2.1 : illustration of vref(dc) tolerance and vref ac-noise limits > the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref " shall be understood as vref(dc), as defined in figure 6.2.1 this clarifies, that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is me asured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum positi on within the data-eye of the input signals. this also clarifies that the dram setup/ hold specification and derating values need to include time and voltage associ - ated with vref ac-noise. timing and volt age effects due to ac-noise on vref up to the specified limit (+/-1% of vdd) are included in dram timings and their associated deratings. 5.2.2 dc & ac logic input leve ls for differential signals note1: refer to ?overshoot and undershoot specification section 6.5 on 26 page symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max vihdiff differential input logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.2 / jul. 2008 17 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.2.3 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters wi th respect to clock and strobe, each cross point voltage of differential inpu t signals (ck, ck# and dqs, dqs#) must meet the requirements in table 6.2.3 the differential input cross point voltage vix is measured from the actual cross point of tr ue and complement signal to the midlevel between of vdd and vss. < figure 5.2.3 vix definition > < table 5.2.3 : cross point voltage for di fferential input signals (ck, dqs) > symbol parameter ddr3-800, ddr3-1066, ddr3-1333, ddr3-1600 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 + 150 mv vdd vss vdd/2 v ix v ix v ix ck#, dqs# ck, dqs
rev. 0.2 / jul. 2008 18 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.3 slew rate definitions 5.3.1 for single ended input signals - input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih(ac)min. setup (tis and tds) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vref and the first crossing of vil(ac)max. - input slew rate for input hold ti me (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih( dc)min and the first crossing of vref. < table 5.3.1 : single-ended input slew rate definition > description measured defined by applicable for min max input slew rate for rising edge vref vih(ac)min vih(ac)min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil(ac)max vref-vil(ac)max delta tfs input slew rate for rising edge vil(dc)max vref vref-vil(dc)max delta tfh hold (tih, tdh) input slew rate for falling edge vih(dc)min vref vih(dc)min-vref delta trh delta tfs delta trs vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca part a: set up single ended input voltage(dq,add, cmd)
rev. 0.2 / jul. 2008 19 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c < figure 5.3.1 : input nominal slew rate definition for single-ended signals > 5.3.2 differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown in below ta b l e and figure . note: the differential signal (i.e. ck-ck and dqs-dq s) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff part b: hold delta tfh delta trh vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca single ended input voltage(dq,add, cmd)
rev. 0.2 / jul. 2008 20 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c < figure 5.3.2 : differential input slew ra te definition for dqs,dqs# and ck,ck# > 5.4 dc & ac output buffer levels 5.4.1 single ended dc & ac output levels below table shows the output levels used for measurements of single ended signals. symbol parameter ddr3-800, 1066, 1333 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of wu 1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. delta tfdiff delta trdiff vihdiffm in vildiffm ax 0 differential input voltage (i.e. dqs-dqs; ck-ck)
rev. 0.2 / jul. 2008 21 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.4.2 differential dc & ac output levels below table shows the output levels used for measurements of differential signals. 5.4.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ende d signals as shown in belo w table and figure 6.4.3. note: output slew rate is verified by design and characte risation, and may not be subject to production test. < figure 5.4.3 : single ended output slew rate definition > symbol parameter ddr3-800, 1066, 1333 unit notes vohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff (ac) ac differential output low measurement level (for outtput sr) - 0.2 x vddq v 1 1. the swing of ? 0.2 x vddq is based on appro ximately 50% of the static differential output high or low swingwith a driver impeda nce of 40?? and an effective test load of 25?? to vtt = vddq/2 at each of the differential output description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse delta tfse delta trse voh(ac) vol(ac) v single ended output voltage(l.e.dq)
rev. 0.2 / jul. 2008 22 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c *** description : sr : slew rate q: query output ( like in dq , which stands for data-in, query-output) for ron = rzq/7 setting < table 5.4.3 : output slew rate (single-ended) > 5.4.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and mea - sured between voldiff(ac) and vohdiff(ac) fo r differential signals as shown in below ta b l e and figure 5.4.4 note: output slew rate is verified by design and charac terization, and may not be subject to production test.. < figure 5.4.4 : differential output slew rate definition > parameter symbol ddr3-800 ddr3-1066 ddr3-1333 units min max min max min max single-ended output slew rate srqse 2.5 5 2.5 5 2.5 5 v/ns description measured defined by from to differential output slew rate for rising edge voldiff(ac) vohdiff(ac) vohdiff(ac)-voldiff(ac) deltatrdiff differential output slew rate for falling edge vohdiff(ac) voldiff(ac) vohdiff(ac)-voldiff(ac) deltatfdiff delta tfdiff delta trdiff voldiff(ac) o differential output voltage(i.e. dqs-dqs) vohdiff(ac)
rev. 0.2 / jul. 2008 23 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c ***description : sr : slew rate q : query output ( like in dq, which stands for data-in, query-output) diff : differential signals for ron = rzq/7 setting < table 5.4.4 : differential output slew rate > 5.5 overshoot and undershoot specifications 5.5.1 address and control overshoot and undershoot specifications < table 5.5.1 : ac overshoot/undershoot spec ification for address and control pins > < figure 5.5.1 : address and control ov ershoot and undershoot definition > parameter symbol ddr3-800 ddr3-1066 ddr3-1333 units min max min max min max differential output slew rate srqdiff 5 10 5 10 5 10 v/ns description specification ddr3-800 ddr3-1066 ddr3-1333 maximum peak amplitude allowed for
rev. 0.2 / jul. 2008 24 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.5.2 clock,data,strobe and mask over shoot and undershoot specifications < table 5.5.2 : ac overshoot/undershoot specif ication for clock, data, strobe and mask > < figure 5.5.2 : clock, data, strobe and ma sk overshoot and undershoot definition > description specification ddr3-800 ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns maximum undershoot area below vssq (see figure) 0.25 v-ns 0.19 v-ns 0.15 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.2 / jul. 2008 25 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.6 pin capacitance parameter symbol ddr3-800 ddr3-1066 ddr3-1333 units notes min max min max min max input/output capacitance (dq, dm, dqs, dqs#, tdqs, tdqs#) c io tbd tbd tbd tbd tbd tbd pf 1,2,3 input capacitance, ck and ck# c ck tbd tbd tbd tbd tbd tbd pf 2,3,5 input capacitance delta ck and ck# c dck tbd tbd tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i tbd tbd tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs# c ddqs tbd tbd tbd tbd tbd tbd pf 2,3,12 input capacitance delta (all ctrl input-only pins) c di_ctrl tbd tbd tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_c md tbd tbd tbd tbd tbd tbd pf 2,3,9,1 0 input/output capacitance delta (dq, dm, dqs, dqs#) c dio tbd tbd tbd tbd tbd tbd pf 2,3,11 notes: 1. tdqs/tdqs# are not necessarily input function but since tdqs is sharing dm pin and the parasitic characterization of tdqs/tdqs# should be close as much as possible, cio&cdio requirement is applied (recommend deleting note or changing to ?although the dm, tdqs and tdqs# pins have different functions, the loading matches dq and dqs.?) 2. this parameter is not subject to production test. it is verified by design and characte rization. input capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector net - work analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck #. 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk#)) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras#, cas# and we#. 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs#)) 12. absolute value of c io (dqs) - c io (dqs#)
rev. 0.2 / jul. 2008 26 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.7 idd specifications(t case : 0 to 95 o c) 512mb, 64m x 64 so-dimm : hmt164s6afp6 c 1gb, 128m x 64 so-dimm : hmt112s6afp6 c symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 360 420 480 ma idd1 480 540 620 ma idd2p(f) 100 120 140 ma idd2p(s) 40 40 40 ma idd2q 180 240 280 ma idd2n 200 240 300 ma idd3p 140 180 200 ma idd3n 220 280 340 ma idd4w 700 880 1060 ma idd4r 700 860 1020 ma idd5b 740 780 840 ma idd6(d) 40 40 40 ma 1 idd6(s) 24 24 24 ma 1 idd7 1300 1420 1720 ma symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 560 660 780 ma idd1 680 780 960 ma idd2p(f) 200 240 280 ma idd2p(s) 80 80 80 ma idd2q 360 480 560 ma idd2n 400 480 600 ma idd3p 280 360 400 ma idd3n 440 560 680 ma idd4w 900 1120 1360 ma idd4r 900 1100 1320 ma idd5b 940 1020 1140 ma idd6(d) 80 80 80 ma 1 idd6(s) 48 48 48 ma 1 idd7 1500 1660 2020 ma
rev. 0.2 / jul. 2008 27 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 2gb, 256m x 64 so-dimm : hmt125s6afp8 c symbol ddr3 800 ddr3 1066 ddr3 1333 unit note idd0 1040 1240 1440 ma idd1 1160 1360 1560 ma idd2p(f) 400 480 560 ma idd2p(s) 160 160 160 ma idd2q 720 960 1120 ma idd2n 800 960 1200 ma idd3p 560 720 800 ma idd3n 880 1120 1360 ma idd4w 1520 1920 2160 ma idd4r 1440 1800 2280 ma idd5b 1880 2040 2320 ma idd6(d) 160 160 160 ma 1 idd6(s) 96 96 96 ma 1 idd7 2200 2480 3040 ma
rev. 0.2 / jul. 2008 28 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 5.7 idd measurement conditions within the tables provided furt her down, an overview about the idd measurement conditions is provided as follows: within the tables about idd measurement cond itions, the following definitions are used: - low is defined as vin <= vilac(max.); high is defined as vin >= vihac(min.). - stable is defined as inputs are stable at a high or low level. - floating is defined as inputs are vref = vddq / 2. - switching is defined as described in the following 2 tables. table 1 ? overview of tables providing idd measurement conditions and dram behavior table number measurement conditions table 5 on page 33 idd0 and idd1 table 6 on page 36 idd2n, idd2q, idd2p(0), idd2p(1) table 7 on page 38 idd3n and idd3p table 8 on page 39 idd4r, idd4w, idd7 table 9 on page 42 idd7 for different speed grades and different trrd, tfaw conditions table 10 on page 43 idd5b table 11 on page 44 idd6, idd6et table 2 ? definition of switching for address and command input signals switching for address (row, column) and command signals ( cs , ras , cas , we ) is defined as: address (row, column) : if not otherwise mentioned the inputs are stable at high or low during 4 clocks and change then to the opposite value (e.g. ax ax ax ax ax ax ax ax ax ax ax ax ..... please see each iddx definition for details bank address : if not otherwise mentioned the bank addresse s should be switched like the row/column addresses - please see each iddx definition for details command ( cs , ras , cas , we ): define d = { cs , ras , cas , we } := {high, low, low, low} define d = { cs , ras , cas , we } := {high, high,high,high} define command background pattern = d d d d d d d d d d d d ... if other commands are necessary (e.g. act for idd0 or read for idd4r), the background pattern command is substi tuted by the respective cs , ras , cas , we levels of the necessary command. see each iddx definition for details and figures 1,2,3 as examples.
rev. 0.2 / jul. 2008 29 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c timing parameters are listed in the following table: the following conditions apply: - idd specifications are tested after the device is properly initialized. - input slew rate is specified by ac parametric test conditions. - idd parameters are specified with odt an d output buffer disabled (mr1 bit a12). table 3 ? definition of switching for data (dq) switching for data (dq) is defined as data (dq) data dq is changing between high and low ev ery other data transfer (once per clock) for dq signals, which means that data dq is stable during one clock; see each iddx definition for exceptions from this rule and for further details. see figures 1,2,3 as examples. data masking (dm) no switching; dm must be driven low all the time table 4 ? for idd testing the foll owing parameters are utilized. parameter bin ddr3-800 ddr3-1066 ddr3-1333 unit 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 t ckmin (idd) 2.5 1.875 1.5 ns cl(idd) 5 6 6 7 8 7 8 9 clk t rcdmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns t rcmin (idd) 50 52.5 48.75 50.63 52.50 46.5 48 49.5 ns t rasmin (idd) 37.5 37.5 37.5 37.5 37.5 36 36 36 ns t rpmin (idd) 12.5 15 11.25 13.13 15 10.5 12 13.5 ns t faw (idd) x4/x8 40 40 37.5 37.5 37.5 30 30 30 ns x16 50 50 50 50 50 45 45 45 ns t rrd (idd) x4/x8 10 10 7.5 7.5 7.5 6.0 6.0 6.0 ns x16 10 10 10 10 10 7.5 7.5 7.5 ns t rfc (idd) - 512mb 90 90 90 90 90 90 90 90 ns t rfc (idd) - 1 gb 110 110 110 110 110 110 110 110 ns t rfc (idd) - 2 gb 160 160 160 160 160 160 160 160 ns t rfc (idd) - 4 gb tbd tbd tbd tbd tbd tbd tbd tbd ns
rev. 0.2 / jul. 2008 30 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 5 ? idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge measurement condition timing diagram example figure 1 cke high high external clock on on t ck t ckmin (idd) t ckmin (idd) t rc t rcmin (idd) t rcmin (idd) t ras t rasmin (idd) t rasmin (idd) t rcd n.a. t rcdmin (idd) t rrd n.a. n.a. cl n.a. cl(idd) al n.a. 0 cs high between. activate and precharge commands high between activate, read and precharge command inputs ( cs , ras , cas , we ) switching as described in table 2 only exceptions are activate and precharge commands; example of idd0 pattern: a0 d dd dd dd dd dd dd d p0 (ddr3-800: t ras = 37.5ns between (a)ctivate and (p)recharge to bank 0; definition of d and d : see table 2 switching as described in table 2; only exceptions are activate, read and precharge commands; example of idd1 pattern: a0 d dd d r0 dd dd dd dd d p0 (ddr3-800 -555: t rcd = 12.5ns between (a)ctivate and (r)ead to bank 0 ; definition of d and d : see table 2)
rev. 0.2 / jul. 2008 31 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c row, column afddresses row addresses switching as described in table 2; address input a10 must be low all the time! row addresses switching as described in table 2; address input a10 must be low all the time! bank addresses bank address is fixed (bank 0) bank address is fixed (bank 0) data i/o switching as described in table 3 read data: output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma, the output buffer should be switched off by mr1 bit a12 set to ?1?. when there is no read data burst from dram, the dq i/o should be floating. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. 8 fixed / mr0 bits [a1, a0] = {0,0} active banks one act-pre loop one act-rd-pre loop idle banks all other all other precharge power down mode / mode register bit 12 n.a. n.a. table 5 ? idd measurement conditions for idd0 and idd1 current i dd0 i dd1 name operating current 0 -> one bank activate -> precharge operating current 1 -> one bank activate -> read -> precharge
rev. 0.2 / jul. 2008 32 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c < figure 1. idd1 example > (ddr3-800-555, 512mb x8): data dq is shown but the output buffer should be switched off (per mr1 bit a12 =?1?) to ac hieve iout = 0ma. address inputs are split into 3 parts. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t12 t14 t16 t18 3ff 000 3ff 000 3f 000 000 11 00 11 00 00 act d# d d# rd d d# d# d d d# d# d d d# pre d d d# 0 0 1 1 0 0 1 1 ck ba[2:0] addr_a[9:0] addr_b[10] addr_c[12:11] cs ras cas we cmd dq dm idd1 measurment loop
rev. 0.2 / jul. 2008 33 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 6 ? idd measurement conditions for idd2n, idd2p(1), idd2p(0) and idd2q current i dd2n i dd2p (1) a a. i dd2p (0) i dd2q name precharge standby current precharge power down current fast exit - mrs a12 bit = 1 precharge power down current slow exit - mrs a12 bit = 0 precharge quiet standby current measurement condition timing diagram example figure 2 cke high low low high external clock on on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. n.a. n.a. t ras n.a. n.a. n.a. n.a. t rcd n.a. n.a. n.a. n.a. t rrd n.a. n.a. n.a. n.a. cl n.a. n.a. n.a. n.a. al n.a. n.a. n.a. n.a. cs high stable stable high bank address, row addr. and command inputs switching as described in table 2 stable stable stable data inputs switching floating floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. n.a. n.a. active banks none none none none idle banks all all all all precharge power down mode / mode register bit a n.a. fast exit / 1 (any valid command after txp b ) b. slow exit / 0 slow exit (rd and odt commands must satisfy txpdll-al) n.a. a. in ddr3, the mrs bit 12 defines dll on/off behaviou r only for precharge power down. there are 2 different precharge power down states possible: one with dll on (fast exit, bit 12 = 1) and one with dll off (slow exit, bit 12 = 0). b. because it is an exit after precharge power down, the valid commands are: activate, refresh, mode-register set, enter - self refresh
rev. 0.2 / jul. 2008 34 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c

(ddr3-800-555, 512mb x8) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 7 0 0 7 0 0 d# d# d d d# d# d d d# d# ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff ck ba[2:0] addr[12:0] cs ras cas we cmd dq[7:0] dm
rev. 0.2 / jul. 2008 35 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 7 ? i dd measurement conditions fo r idd3n and idd3p(fast exit) current i dd3n i dd3p name active standby current active power-down current a always fast exit a. ddr3 will offer only one active power down mode with dll on (-> fast exit). mrs bit 12 will not be used for active power down. instead bit 12 will be used to sw itch between two different precharge power down modes. measurement condition timing diagram example figure 2 cke high low external clock on on t ck t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs high stable addr. and cmd inputs switching as described in table 2 stable data inputs switching as described in table 3 floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all all idle banks none none precharge power down mode / mode register bit a n.a. n.a. (active power down mode is always ?fast exit? with dll on
rev. 0.2 / jul. 2008 36 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 8 ? idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current measurement condition timing diagram example figure 3 cke high high high external clock on on on t ck t ckmin (idd) t ckmin (idd) t ckmin (idd) t rc n.a. n.a. t rcmin (idd) t ras n.a. n.a. t rasmin (idd) t rcd n.a. n.a. t rcdmin (idd) t rrd n.a. n.a. t rrdmin (idd) cl cl(idd) cl(idd) cl(idd) al 0 0 t rcdmin - 1 t ck cs high btw. valid cmds high btw. valid cmds high btw. valid cmds command inputs ( cs , ras , cas , we ) switching as described in table 2; exceptions are read commands => idd4r pattern: r0 d dd r1 d dd r2 d dd r3 .d dd r4 ..... rx = read from bank x; definition of d and d : see table 2 switching as described in table 2 ; exceptions are write commands => idd4w pattern: w0 d dd w1 d dd w2 d dd w3 d dd w4 ... wx = write to bank x; definition of d and d : see table 2 for patterns see table 9
rev. 0.2 / jul. 2008 37 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c row, colum addresses column addresses switching as described in table 2 ; address input a10 must be low all the time! column addresses switching as described in table 2 ; address input a10 must be low all the time! stable during deselects bank addresses bank address cycling (0 -> 1 - > 2 -> 3 ...) bank address cycling (0 -> 1 - > 2 -> 3 ...) bank address cycling (0 -> 1 - > 2 -> 3 ...), see pattern in table 9 dq i/o seamless read data burst (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. seamless write data burst (bl8): input data switches every clock, wh ich means that write data is stable during one clock cycle. dm is low all the time. read data (bl8): output data switches every clock, which means that read data is stable during one clock cycle. to achieve iout = 0ma the output buffer should be switched off by mr1 bit a12 set to ?1?. output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] disabled / [0,0] burst length 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} 8 fixed / mr0 bits [a1, a0] = {0,0} active banks all all all, rotational idle banks none none none precharge power down mode / mode register bit n.a. n.a. n.a. table 8 ? idd measurement conditions for idd4r, idd4w and idd7 current i dd4r i dd4w i dd7 name operating current burst read operating current burst write all bank interleave read current
rev. 0.2 / jul. 2008 38 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c < figure 3. idd4r example > (ddr3-800-555, 512mb x8): data dq is shown but the output buffer should be switched off (per mr1 bi t a12=?1?) to achieve iout = 0ma. address inputs are split into 3 parts. t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 001 010 011 00 00 ff ff 00 00 ff ff 00 00 ff ff 00 00 ff ff ck ba[2:0] addr[12:0] cs ras cas we cmd[2:0] dq[7:0] dm t10 t11 t12 3ff 000 3ff addr_b[10] 11 00 11 addr_c[12:11] 000 000 00 rd d d# d# rd d d# d# d# rd d# rd d -> start of measurement loop
rev. 0.2 / jul. 2008 39 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 9 ? idd7 pattern for different speed grades and different trrd, tfaw conditions speed bin org. tfaw tfaw trrd trrd idd7 pattern a a. a0 = activation of bank 0; ra0 = read with auto-precharge of bank 0; d = deselect mb/s [ns] [clk] [ns] [clk] (note this entire sequence is repeated.) 800 all x4/x8 40 16 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d all x16 50 20 10 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d 1066 all x4/x8 37.5 20 7.5 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 50 27 10 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d 1333 all x4/x8 30 20 6 4 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d a4 ra4 d d a5 ra5 d d a6 ra6 d d a7 ra7 d d d d d d all x16 45 30 7.5 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d d d d d d d 1600 all x4/x8 30 24 6 5 a0 ra0 d d d a1 ra1 d d d a2 ra2 d d d a3 ra3 d d d d d d d a4 ra4 d d d a5 ra5 d d d a6 ra6 d d d a7 ra7 d d d d d d d all x16 40 32 7.5 6 a0 ra0 d d d d a1 ra1 d d d d a2 ra2 d d d d a3 ra3 d d d d d d d d d d d d a4 ra4 d d d d a5 ra5 d d d d a6 ra6 d d d d a7 ra7 d d d d d d d d d d d d
rev. 0.2 / jul. 2008 40 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 10 ? idd measuremen t conditions for idd5b current i dd5b name burst refresh current measurement condition cke high external clock on t ck t ckmin (idd) t rc n.a. t ras n.a. t rcd n.a. t rrd n.a. t rfc t rfcmin (idd) cl n.a. al n.a. cs high btw. valid cmds addr. and cmd inputs switching data inputs switching output buffer dq,dqs / mr1 bit a12 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] burst length n.a. active banks refresh command every trfc=trfcmin idle banks none precharge power down mode / mode register bit n.a.
rev. 0.2 / jul. 2008 41 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c table 11 ? idd measurement co nditions for idd6 and idd6et current i dd6 i dd6et name self-refresh current normal temperature range t case = 0 .. 85 c self-refresh current extended temperature range a t case = 0 .. 95 c a. users should refer to the dram supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the following options or requirements referred to in this material. measurement condition temperature t case = 85 c t case = 95 c auto self refresh (asr) / mr2 bit a6 disabled / ?0? disabled / ?0? self refresh temperature range (srt) / mr2 bit a7 normal / ?0? extended / ?1? cke low low external clock off; ck and ck at low off; ck and ck at low t ck n.a. n.a. t rc n.a. n.a. t ras n.a. n.a. t rcd n.a. n.a. t rrd n.a. n.a. cl n.a. n.a. al n.a. n.a. cs floating floating command inputs ( ras , cas , we ) floating floating row, colum addresses floating floating bank addresses floating floating data i/o floating floating output buffer dq,dqs / mr1 bit a12 off / 1 off / 1 odt / mr1 bits [a6, a2] disabled / [0,0] disabled / [0,0] burst length n.a. n.a. active banks all during self-refresh actions all during self-refresh actions idle banks all btw. self-refresh actions all btw. self-refresh actions precharge power down mode / mr0 bit a12 n.a. n.a.
rev. 0.2 / jul. 2008 42 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 6 . electrical characteristics and ac timing 6.1 refresh parameters by device density 6.2 ddr3 sdram standard speed bins includ e tck, trcd, trp, tr as and trc for each corresponding bin parameter symbol 512mb 1gb 2gb 4gb 8gb units ref command to act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c < t case < 85 c 7.8 7.8 7.8 7.8 7.8 ms 85 c < t case < 95 c 3.9 3.9 3.9 3.9 3.9 ms ddr3 800 speed bin ddr3-800d ddr3-800e unit notes cl - nrcd - nrp 5-5-5 6-6-6 parameter symbol min max min max internal read command to first data t aa 12.5 20 15 20 ns act to internal read or write delay time t rcd 12.5 ? 15 ? ns pre command period t rp 12.5 ? 15 ? ns act to act or ref command period t rc 50 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved ns 1)2)3)4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 ns 1)2)3) supported cl settings 5, 6 6 n ck supported cwl settings 55 n ck
rev. 0.2 / jul. 2008 43 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c ddr3 1066 speed bin ddr3-1066e ddr3-1066f ddr3-1066g unit note cl - nrcd - nrp 6-6-6 7-7-7 8-8-8 parameter symbol min max min max min max internal read command to first data t aa 11.25 20 13.125 20 15 20 ns act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15 ? ns pre command period t rp 11.25 ? 13.125 ? 15 ? ns act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns act to pre command period t ras 37.5 9 * trefi 37.5 9 * trefi 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 reserved reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved reserved reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved reserved reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1)2)3) supported cl settings 5, 6, 7, 8 6, 7, 8 6, 8 n ck supported cwl settings 5, 6 5, 6 5, 6 n ck
rev. 0.2 / jul. 2008 44 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c ddr3 1333 speed bin ddr3-1333f (optional) ddr3-1333g ddr3-1333h ddr3-1333j (optional) unit note cl - nrcd - nrp 7-7-7 8-8-8 9-9-9 10-10-10 parameter symbol min max min max min max min max internal read command to first t aa 10.5 20 12 20 13.5 20 15 20 ns act to internal read or write delay time t rcd 10.5 ? 12 ? 13.5 ? 15 ? ns pre command period t rp 10.5 ? 12 ? 13.5 ? 15 ? ns act to act or ref command period t rc 46.5 ? 48 ? 49.5 ? 51 ? ns act to pre command period t ras 36 9 * trefi 36 9 * trefi 36 9 * trefi 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 reserved reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) 1.875 < 2.5 reserved reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved reserved reserved reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 reserved reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) 1.5 <1.875 reserved reserved reserved ns 1,2,3,4 cl = 8 cwl = 5 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 reserved reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 reserved ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved reserved reserved reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 1.5 <1.875 1.5 <1.875 1.5 <1.875 ns 1,2,3 (optional) (optional) (optional) ns 5 supported cl settings 5, 6, 7, 8, 9 5, 6, 7, 8, 9 6, 8, 9 6, 8, 10 n ck supported cwl settings 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 n ck
rev. 0.2 / jul. 2008 45 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c *speed bin table notes * absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl setting resu lt in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely an alog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be gu aranteed. an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns ) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the result ing tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and sp d information if and how this setting is supported. 6. any ddr3-1066 speed bin also support s functional operation at lower freque ncies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization.
rev. 0.2 / jul. 2008 46 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 7 . dimm outline diagram 7.1 64mx64 - hmt164s6afp(r)6c front view rear view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a detail-b 1.00 0 3.80mm max side 4.00 0.10 2 x 1.8 0.10 1.65 0.10
rev. 0.2 / jul. 2008 47 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 64mx64 - hmt164s6afp (r)6c (with temperature sensor) front view rear view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 spd (ts) 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a detail-b 1.00 0 3.80mm max side 4.00 0.10 2 x 1.8 0.10 1.65 0.10
rev. 0.2 / jul. 2008 48 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 7.2 128mx64 - hm t112s6afp(r)6c front view rear view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 spd 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a detail-b 1.00 0 3.80mm max side 4.00 0.10 2 x 1.8 0.10 1.65 0.10
rev. 0.2 / jul. 2008 49 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 128mx64 - hmt112s6afp(r)6c (with temperature sensor) front view rear view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 spd(ts) 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a detail-b 1.00 0 3.80mm max side 4.00 0.10 2 x 1.8 0.10 1.65 0.10
rev. 0.2 / jul. 2008 50 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 7.3 256mx64 - hm t125s6afp(r)8c front view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 rear view 30.0mm 67.60mm 4.00 0.10 20.0mm 6.00 2.0 21.00 39.00 2.15 1.65 0.10 2x 1.8 0.10 3.00 pin 1 pin 203 detail- a spd 1.00 0 3.80mm max side detail-b
rev. 0.2 / jul. 2008 51 hmt164s6afp(r)6c hmt112s6afp(r)6c hmt125s6afp(r)8c 256mx64 - hmt125s6afp(r)8c (with temperature sensor) front view 0.20 2.55 0. 60 0. 45 0.03 2.55 1. 0 0 0.05 0.3 0. 15 0.3+0.7 3.00 4.00 rear view 30.0mm 67.60mm 4.00 0.10 20.0mm 6.00 2.0 21.00 39.00 2.15 1.65 0.10 2x 1.8 0.10 3.00 pin 1 pin 203 detail- a spd (ts) 1.00 0 3.80mm max side detail-b

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